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--- risc [2026/05/24 08:39] – mrmaxthemac
+++ risc [2026/05/24 11:18] (current) – mrmaxthemac
@@ Line 1: / Line 1: @@
-====== RISC-V ======
+{{ ::risc_cpu_sun_ultrasparc.jpg?direct&200|}}
+====== RISC / RISC-V ======
 ====Reduced Instruction Set Computing 5====
-{{ ::risc_cpu_sun_ultrasparc.jpg?direct&400|}}
->RISC-V is based on the Reduced Instruction Set Computing (RISC) design principle, which emphasizes simplicity and modularity in instruction set architecture.**
+>RISC-V is based on the Reduced Instruction Set Computing (RISC) design principle, which emphasizes simplicity and modularity in instruction set architecture.
+[[arduino_nano|Arduino Nano]] and other ATmega328(p)/4809 are a classic 'Enhanced' RISC architecture - Single core, low clock speed, but one instruction per cycle (extreme efficiency)
+----
 The RISC-V instruction set architecture (ISA) is an open-source, free-to-use, and royalty-free architecture for computer
-processors. Developed by the University of California, Berkeley's Computer Science Division. Development of RISC-V began in 2009 as a research project to create a low-power, high-performance processor that could be used in a wide range of applications. The initial goal was to create an architecture that could be easily modified and customized for specific use cases. Today, RISC-V is widely adopted across various industries, including embedded systems, data centers, and mobile devices.
+processors. Developed by the University of California, Berkeley's Computer Science Division. Development of RISC-V began in 2009 as a research project to create a low-power, high-performance processor that could be used in a wide range of applications.
+{{:risc_in_watch.jpg?nolink&200 |}}
+The initial goal was to create an architecture that could be easily modified and customized for specific use cases. Today, RISC-V is widely adopted across various industries, including embedded systems, data centers, and mobile devices. RISC-V chips power everything from insulin pumps and pacemakers to the specialized AI datacenter processing chips.
@@ Line 16: / Line 21: @@
   * Fixed-length instructions: Instructions have a fixed length, making them easier to decode and execute.
   * Instruction-level parallelism: Instructions can be executed in parallel, improving performance.
-{{ ::riscv_cpu_esp32_s2.jpg?direct&200|esp32s2}}
-**RISC-V's Relationship with the ESP32 Family**
+----
-The ESP32 family of microcontrollers, developed by Espressif Systems, uses the RISC-V architecture for its processor core.
+{{ :esp32_c3_cpu.jpg?nolink&325|}}
+**RISC-V's Relationship with [[esp32|the ESP32 Family]]**
+The [[esp32|ESP32 family]] of [[microcontroller|microcontrollers]], developed by [[espressif|Espressif Systems]], uses the [[risc|RISC-V]] architecture for its processor core.
 Specifically:
-  * __ESP32-S2:__ single-core 16-bit RISC-V processor.
+  * __[[esp32c2|ESP32-C2]]:__  single core 32-bit [[risc|RISC-V]] processor.
-  * __ESP32-C3:__ dual-core 32-bit RISC-V processor.
+  * __[[esp32c3|ESP32-C3]]:__  single core 32-bit [[risc|RISC-V]] processor.
-  * __ESP32-C6:__ dual-core 32-bit RISC-V processor.
+  * __[[esp32c5|ESP32-C5]]:__    dual core 32-bit [[risc|RISC-V]] split speed processor (1 performance core, 1 efficiency core).
+  * __[[esp32c6|ESP32-C6]]:__    dual core 32-bit [[risc|RISC-V]] split speed processor (1 performance core, 1 efficiency core).
+  * __[[esp32h2|ESP32-H2]]:__  single core 32 bit [[risc|RISC-V]] processor.
+  * __[[esp32p4|ESP32-P4]]:__   three core 32 bit [[risc|RISC-V]] split speed processor (2 performance cores, 1 efficiency core).
+----
+//These systems DO NOT have a RISC-V CPU, but have XTENSA architecture instead://
+  *<del>[[esp32wroom1|ESP32 (original)]]</del>
+  *<del>[[esp32s2|ESP32-S2]]</del>
+  *<del>[[esp32s3|ESP32-S3]]</del>
 The use of RISC-V in the ESP32 family provides several benefits, including: