Differences

This shows you the differences between two versions of the page.

--- risc [2026/05/24 09:09] – mrmaxthemac
+++ risc [2026/05/24 11:18] (current) – mrmaxthemac
@@ Line 1: / Line 1: @@
-====== RISC-V ======
-====Reduced Instruction Set Computing 5====
 {{ ::risc_cpu_sun_ultrasparc.jpg?direct&200|}}
+====== RISC / RISC-V ======
+====Reduced Instruction Set Computing 5====
 >RISC-V is based on the Reduced Instruction Set Computing (RISC) design principle, which emphasizes simplicity and modularity in instruction set architecture.
-Arduino Nano and other ATmega328(p)/4809 are a classic 'Enhanced' RISC architecture
+[[arduino_nano|Arduino Nano]] and other ATmega328(p)/4809 are a classic 'Enhanced' RISC architecture - Single core, low clock speed, but one instruction per cycle (extreme efficiency)
 ----
@@ Line 21: / Line 21: @@
   * Fixed-length instructions: Instructions have a fixed length, making them easier to decode and execute.
   * Instruction-level parallelism: Instructions can be executed in parallel, improving performance.
-{{ ::riscv_cpu_esp32_s2.jpg?direct&200|esp32s2}}
 ----
+{{ :esp32_c3_cpu.jpg?nolink&325|}}
-**RISC-V's Relationship with the ESP32 Family**
+**RISC-V's Relationship with [[esp32|the ESP32 Family]]**
-The ESP32 family of microcontrollers, developed by Espressif Systems, uses the RISC-V architecture for its processor core.
+The [[esp32|ESP32 family]] of [[microcontroller|microcontrollers]], developed by [[espressif|Espressif Systems]], uses the [[risc|RISC-V]] architecture for its processor core.
 Specifically:
-  * __ESP32-C2:__  single core 32-bit RISC-V processor.
+  * __[[esp32c2|ESP32-C2]]:__  single core 32-bit [[risc|RISC-V]] processor.
-  * __ESP32-C3:__  single core 32-bit RISC-V processor.
+  * __[[esp32c3|ESP32-C3]]:__  single core 32-bit [[risc|RISC-V]] processor.
-  * __ESP32-C5:__    dual core 32-bit RISC-V split speed processor (1 performance core, 1 efficiency core).
+  * __[[esp32c5|ESP32-C5]]:__    dual core 32-bit [[risc|RISC-V]] split speed processor (1 performance core, 1 efficiency core).
-  * __ESP32-C6:__    dual core 32-bit RISC-V split speed processor (1 performance core, 1 efficiency core).
+  * __[[esp32c6|ESP32-C6]]:__    dual core 32-bit [[risc|RISC-V]] split speed processor (1 performance core, 1 efficiency core).
-  * __ESP32-H2:__  single core 32 bit RISC-V processor.
+  * __[[esp32h2|ESP32-H2]]:__  single core 32 bit [[risc|RISC-V]] processor.
-  * __ESP32-P4:__   three core 32 bit RISC-V split speed processor (2 performance cores, 1 efficiency core).
+  * __[[esp32p4|ESP32-P4]]:__   three core 32 bit [[risc|RISC-V]] split speed processor (2 performance cores, 1 efficiency core).
+----
-//These systems DO NOT have a RISC-V CPU, but have XTENSA architecture instead//
+//These systems DO NOT have a RISC-V CPU, but have XTENSA architecture instead://
   *<del>[[esp32wroom1|ESP32 (original)]]</del>
   *<del>[[esp32s2|ESP32-S2]]</del>